High Speed Latch Comparators

ABSTRACT

In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.12/040,805, filed Feb. 29, 2008, which is a divisional of U.S.application Ser. No. 10/649,808, filed Aug. 28, 2003, now U.S. Pat. No.7,352,215, which is a continuation of U.S. application Ser. No.10/083,463, filed Feb. 27, 2002, now U.S. Pat. No. 6,639,430, whichclaims the benefit of U.S. Provisional Application No. 60/271,425, filedFeb. 27, 2001, all of which are incorporated herein in its entirety byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to high speed latch comparators.

2. Background Art

Commercialization of the Internet has proven to be a mainspring forincentives to improve network technologies. Development programs havepursued various approaches including strategies to leverage use of theexisting Public Switched Telephone Network and plans to expand use ofwireless technologies for networking applications. Both of theseapproaches (and others) entail the conversion of data between analog anddigital formats. Therefore, it is expected that analog-to-digitalconverters (ADCs) and digital-to-analog converters (DACs) will continueto perform critical functions in many network applications.

Because ADCs find uses in a wide variety of applications, design ofthese circuits has evolved along many paths to yield several distinctarchitectures, including “delta sigma,” “successive approximation,”“pipelined,” and “flash.” Each architecture has its benefits anddrawbacks. Paramount among these is a tradeoff between bandwidth anddegree of resolution. FIG. 1 is a graph 100 that shows the tradeoffbetween bandwidth and degree of resolution for the various ADCarchitectures. Graph 100 comprises a “degree of resolution” axis 102 anda “bandwidth” axis 104. The relative positions of the different ADCarchitectures are plotted with respect to axes 102, 104: a “delta sigma”region 106, a “successive approximation” region 108, a “pipelined”region 110, and a “flash” region 112. In the design of networktechnologies, data conversion has often presented itself as a bottleneckthat impedes the rate at which information is transmitted. Therefore,those ADC architectures that can support large bandwidths for rapidtransfers of data have been favored for network applications.

FIG. 2A is a block diagram of an exemplary conventional two-bit flashADC 200. ADC 200 comprises a first comparator “A” 202, a secondcomparator “B” 204, a third comparator “C” 206, a priority encoder 208,a first resistor “R₁” 210, a second resistor “R₂” 212, a third resistor“R₃” 214, and a fourth resistor “R₄” 216. Each of R₁ 210, R₂ 212, R₃214, and R₄ 216 has the same measure of resistance. R₁ 210, R₂ 212, R₃214, and R₄ 216 are connected in series between an analog ground“V_(AG)” 218 and a supply voltage “V” 220. R₁ 210 is connected betweenV_(AG) 218 and a first node “N₁” 222. R₂ 212 is connected between N₁ 222and a second node “N₂” 224. R₃ 214 is connected between N₂ 224 and athird node “N₃” 226. R₄ 216 is connected between N₃ 226 and V 220. Inthis configuration, the voltage at N₁ 222 is equal to V/4, the voltageat N₂ 224 is equal to V/2, and the voltage at N₃ 226 is equal to 3V/4.

The inverting terminals of comparators A 202, B 204, and C 206 areconnected to, respectively, N₁ 222, N₂ 224, and N₃ 226. An analog signal“x” 228 is received at an input 230, which is connected to thenoninverting terminals of comparators A 202, B 204, and C 206. Aquantized signal is produced at the output terminal of each comparator.Quantized signals “w₁” 232, “w₂” 234, and “w₃” 236 are produced at theoutput terminals of, respectively, comparators A 202, B 204, and C 206.Each quantized signal has a voltage with a value “LOW” or a value “HIGH”depending upon whether a corresponding value of the voltage of analogsignal x 228 is less than (or equal to) or greater than the voltage atthe inverting terminal of the corresponding comparator (i.e., thereference voltage of the comparator). For example, when the value of thevoltage of analog signal x 228 is less than or equal to V/4, the valuesof the voltages of w₃ 236, w₂ 234, and w₁ 232 are equal to,respectively, LOW, LOW, and LOW. When the value of the voltage of analogsignal x 228 is less than or equal to V/2, but greater than V/4, thevalues of the voltages of w₃ 236, w₂ 234, and w₁ 232 are equal to,respectively, LOW, LOW, and HIGH. When the value of the voltage ofanalog signal x 228 is less than or equal to 3V/4, but greater than V/2,the values of the voltages of w₃ 236, w₂ 234, and w₁ 232 are equal to,respectively, LOW, HIGH, and HIGH. When the value of the voltage ofanalog signal x 228 is less than or equal to V, but greater than 3V/4,the values of the voltages of w₃ 236, w₂ 234, and w₁ 232 are equal to,respectively, HIGH, HIGH, and HIGH. It is because quantized signals w₁232, w₂ 234, and w₃ 236 are produced simultaneously that two-bit flashADC 200, also referred to as a “parallel-comparator” ADC, is capable ofsupporting large bandwidths for rapid transfers of data.

The output terminals of comparators A 202, B 204, and C 206 areconnected to priority encoder 208. Quantized signals w₁ 232, w₂ 234, andw₃ 236 are received by priority encoder 208, which processes them toproduce, at an output 238, a two-bit digital signal “y” comprising aleast significant bit (LSB) signal “y₁” 240 and a most significant bit(MSB) signal “y₂” 242. FIG. 2B is a truth table 244 for priority encoder208. In truth table 244, LOW and HIGH are encoded as, respectively, 0and 1. When quantized signals w₃ 236, w₂ 234, and w₁ 232 are equal to,respectively, 0, 0, and 0, bit signals y₂ 242 and y₁ 240 are equal to,respectively, 0 and 0, which corresponds to binary number 0. Whenquantized signals w₃ 236, w₂ 234, and w₁ 232 are equal to, respectively,0, 0, and 1, bit signals y₂ 242 and y₁ 240 are equal to, respectively, 0and 1, which corresponds to binary number 1. When quantized signals w₃236, w₂ 234, and w₁ 232 are equal to, respectively, 0, 1, and 1, bitsignals y₂ 242 and y₁ 240 are equal to, respectively, 1 and 0, whichcorresponds to binary number 2. When quantized signals w₃ 236, w₂ 234,and w₁ 232 are equal to, respectively, 1, 1, and 1, bit signals y₂ 242and y₁ 240 are equal to, respectively, 1 and 1, which corresponds tobinary number 3.

The skilled artisan will appreciate that, with additional comparatorsand resistors and by using a priority encoder capable of processingadditional quantized signals, flash ADC 200 can be modified so thatdigital signal y comprises more than two bit signals. Alternatively,flash ADC 200 can be modified so that digital signal y comprises one bitsignal.

Implementations of comparators A 202, B 204, and C 206 often use latchcircuits, and are referred to as latch comparators. FIG. 3 is aschematic diagram of an exemplary conventional latch circuit 300 thatcan be used in an implementation of any of comparators A 202, B 204, orC 206. Latch circuit 300 comprises a bistable pair 302 connected betweena reset switch 304 and analog ground V_(AG) 218. (Alternatively, analogground V_(AG) 218 can be replaced by a first supply voltage “V_(SS)”.)Preferably, bistable pair 302 comprises a first NMOSFET (n-channel MetalOxide Semiconductor Field Effect Transistor) “M₁” 306 and a secondNMOSFET “M₂” 308. Ideally, M₁ 306 and M₂ 308 are matched transistors.Preferably, each of M₁ 306 and M₂ 308 has a gain greater than one.However, bistable pair 302 can function if the product of the individualgains of M₁ 306 and M₂ 308 (i.e., the loop gain) is greater than one.The gate terminal of M₂ 308 is connected to the drain terminal of M₁ 306at a first port “N₄” 310. The gate terminal of M₁ 306 is connected tothe drain terminal of M₂ 308 at a second port “N₅” 312. The sourceterminals of M₁ 306 and M₂ 308 are together connected to analog groundV_(AG) 218. In this configuration, M₁ 306 and M₂ 308 are said to becross connected. Preferably, reset switch 304 comprises a third NMOSFET“M₃” 314. The source terminal of M₃ 314 is connected to the drainterminal of one of M₁ 306 or M₂ 308; the drain terminal of M₃ 314 isconnected the drain terminal of the other of M₁ 306 or M₂ 308. A clockwaveform “Ck” 316 is applied to the gate terminal of M₃ 314. Ck 316cycles between an “UP” voltage and an “DOWN” voltage at a samplingfrequency.

The skilled artisan will appreciate that M₁ 306, M₂ 308, and M₃ 314 canalso be realized in other field effect, junction, or combinationtransistor technologies. In general, reset switch 304 can be realized ina variety of switch technologies, including microelectromechanicalembodiments. Latch circuit 300 can also be used for other applications.

For each latch circuit 300 in ADC 200, quantized signal “w” (e.g., w₁232, w₂ 234, or w₃ 236) is produced as an output voltage at N₄ 310 or N₅312. Latch circuit 300 is often preceded by an input stage (not shown)that includes a differential amplifier so that the voltage of analogsignal x 228, applied at the noninverting terminal of the comparator,can be compared with the voltage at the inverting terminal of thecomparator. For example, the voltage of analog signal x 228 is comparedwith V/4, for comparator A 202; V/2, for comparator B 204; and 3V/4, forcomparator C 206.

The input stage produces a differential current signal comprising afirst current signal “i₁” 318 and a second current signal “i₂” 320.First and second current signals i₁ 318 and i₂ 320 each comprise a biascurrent “i_(b)” and a signal current “i_(s)”. The relationship betweenbias current i_(b) and signal current i_(s) in first current signal i₁318 can be expressed as shown in Eq. (1):

i ₁ =i _(b)+(½)(i _(s)),  Eq. (1)

while the relationship between bias current i_(b) and signal currenti_(s) in second current signal i₂ 320 can be expressed as shown in Eq.(2):

i ₂ =i _(b)−(½)(i _(s)).  Eq. (2)

The differential amplifier is configured so that first current signal i₁318 increases and decreases in response to, respectively, the rise anddrop of the voltage of analog signal x 228, while second current signali₂ 320 increases and decreases in response to, respectively, the dropand rise of the voltage of analog signal x 228. Thus, first and secondcurrent signals i₁ 318 and i₂ 320 always change currents in oppositedirections, but the sum of first and second current signals i₁ 318 andi₂ 320 remains constant. In latch circuit 300, first current signal i₁318 and second current signal i₂ 320 are received as input currentsignals at, respectively, N₄ 310 and N₅ 312.

In latch circuit 300, when the voltage of Ck 316 is UP (i.e, the resetphase), M₃ 314 connects N₄ 310 with N₅ 312, so that the steady statevoltages at both nodes are equal, and bias current i_(b) flows througheach of M₁ 306 and M₂ 308. Parasitic capacitances at each of nodes N₄310 and N₅ 312 are charged by bias current i_(b) that flows through eachof M₁ 306 and M₂ 308. The skilled artisan will appreciate that theparasitic capacitance at, for example, N₄ 310, includes thegate-to-source capacitance of M₂ 308, the drain-to-substrate capacitanceof M₁ 306, the drain-to-substrate capacitance of M₃ 314, and thecapacitance of the wiring connecting circuit devices. Bias current i_(b)charges the parasitic capacitances at each of nodes N₄ 310 and N₅ 312 sothat the voltages at N₄ 310 and N₅ 312 are at a “MID” value that isbetween LOW and HIGH. The gate and drain terminals of M₁ 306 and M₂ 308are connected together. M₁ 306 and M₂ 308 are sized so that, under theseconditions, they operate in “ON” states.

When the voltage of Ck 316 is DOWN (i.e., the sampling phase), thestates of M₁ 306 and M₂ 308 are controlled by first and second currentsignals i₁ 318 and i₂ 320. For example, when first current signal i₁ 318is greater than bias current i_(b) and second current signal i₂ 320 isless than bias current i_(b), a transient is initiated to force M₁ 306to operate in an “OFF” state, while M₂ 308 remains operating in an ONstate. The course of this transient depends on how first and secondcurrent signals i₁ 318 and i₂ 320 change during the sampling phase.However, if M₁ 306 is turned OFF and the parasitic capacitances at N₄310 are fully charged by first current signal i₁ 318 (i.e., at a newsteady state), the voltage at N₄ 310 is HIGH and the voltage at N₅ 312is LOW. The transient can be explained in two parts. The first partdescribes the changes that occur while M₁ 306 remains ON. The secondpart depicts the conclusion of the excursion after M₁ 306 is turned OFF.

When first current signal i₁ 318 is greater than bias current i_(b),first current signal i₁ 318 continues to charge the parasiticcapacitances at N₄ 310, which causes the voltage at N₄ 310 to rise. Thisis indicated by a small up-arrow “a” 322. Contemporaneously, when secondcurrent signal i₂ 320 is less than bias current i_(b), the parasiticcapacitances at N₅ 312 start to discharge, which causes the voltage atN₅ 312 to drop. This is indicated by a small down-arrow “b” 324.

Because the voltage at N₄ 310 is also the voltage at the gate terminalof M₂ 308, the voltage at the gate terminal of M₂ 308 rises by the sameamount as the rise in the voltage at N₄ 310. This is indicated by asmall up-arrow “c” 326, where small up-arrow c 326 has the same length(i.e., the same change in voltage) as small up-arrow a 322. Because thevoltage at the source terminal of M₂ 308 is held at analog ground V_(AG)218, the gate-to-source voltage of M₂ 308 increases by the same amountas the rise in the voltage at the gate terminal of M₂ 308. The increasein the gate-to-source voltage of M₂ 308 causes its drain current toincrease. In response to the increase in the gate-to-source voltage ofM₂ 308 and the increase in its drain current, the drain-to-sourcevoltage of M₂ 308 decreases by a greater magnitude than the increase inits gate-to-source voltage. This is indicated by a large down-arrow “d”328, where large down-arrow d 328 has a longer length (i.e., a largerchange in voltage) than small up-arrow c 326. Because the voltage at thesource terminal of M₂ 308 is held at analog ground V_(AG) 218, thevoltage at N₅ 312 drops by the same amount as the decrease indrain-to-source voltage of M₂ 308. Thus, the voltage at N₅ 312 dropsunder the relatively small effect of second current signal i₂ 320 beingless than bias current i_(b) (i.e., small down-arrow b324), and therelatively large effect of the decrease in the drain-to-source voltageof M₂ 308 (i.e., large down-arrow d 328).

Likewise, because the voltage at N₅ 312 is also the voltage at the gateterminal of M₁ 306, the voltage at the gate terminal of M₁ 306 drops bythe same amount as the drop in the voltage at N₅ 312. This is indicatedby a small down-arrow “e” 330, where small down-arrow e 330 has the samelength (i.e., the same change in voltage) as small down-arrow b 324.Because the voltage at the source terminal of M₁ 306 is held at analogground V_(AG) 218, the gate-to-source voltage of M₁ 306 decreases by thesame amount as the drop in the voltage at the gate terminal of M₁ 306.The decrease in the gate-to-source voltage of M₁ 306 causes its draincurrent to decrease. In response to the decrease in the gate-to-sourcevoltage of M₁ 306 and the decrease in its drain current, thedrain-to-source voltage of M₁ 306 increases by a greater magnitude thanthe decrease in its gate-to-source voltage. This is indicated by a largeup-arrow “f” 332, where large up-arrow f 332 has a longer length (i.e.,a larger change in voltage) than small down-arrow e 330. Because thevoltage at the source terminal of M₁ 306 is held at analog ground V_(AG)218, the voltage at N₄ 310 rises by the same amount as the increase indrain-to-source voltage of M₁ 306. Thus, the voltage at N₄ 310 risesunder the relatively small effect of first current signal i₁ 318 beinggreater than bias current i_(b) (i.e., small up-arrow a 322) and therelatively large effect of the increase in the drain-to-source voltageof M₁ 306 (i.e., large up-arrow f 332).

The increasing of the drain-to-source voltage of M₁ 306 and thedecreasing of the drain-to-source voltage of M₂ 308 reinforce eachother. The gate-to-source voltage of M₁ 306 decreases with thedrain-to-source voltage of M₂ 308 until M₁ 306 is turned OFF.

When M₁ 306 is OFF, it does not conduct current. Without drain current,the decreasing of the gate-to-source voltage of M₁ 306 no longer effectsits drain-to-source voltage. Thus, the voltage at N₄ 310 continues torise solely under the relatively small effect of first current signal i₁318 being greater than bias current i_(b) (i.e., small up-arrow a 322)until the parasitic capacitances at N₄ 310 are fully charged and thevoltage at N₄ 310 is HIGH.

However, because the voltage at N₄ 310 is also the voltage at the gateterminal of M₂ 308, the voltage at the gate terminal of M₂ 308 continuesto rise. Because M₂ 308 remains ON, the increase in its gate-to-sourcevoltage causes the drain current of M₂ 308 to increase, which in turncauses its drain-to-source voltage to decrease by a greater magnitudethan the increase in the gate-to-source voltage of M₂ 308. Thus, thevoltage at N₅ 312 continues to drop under the relatively small effect ofsecond current signal i₂ 320 being less than bias current i_(b) (i.e.,small down-arrow b 324) and the relatively large effect of the decreasein the drain-to-source voltage of M₂ 308 (i.e., large down-arrow d 328)until the discharge of the parasitic capacitances at N₅ 312 is balancedand the voltage at N₅ 312 is LOW.

Therefore, it is a characteristic of latch circuit 300 that the port(i.e., N₄ 310 or N₅ 312) receiving the current signal (i.e., i₁ 318 ori₂ 320) that is greater than bias current i_(b) requires more time toreach its new steady state voltage than the port receiving the currentsignal that is less than bias current i_(b). In practicalimplementations of latch circuit 300, the port receiving the currentsignal that is greater than bias current i_(b) can require three to fivetimes as much time to reach its new steady state voltage as that of theport receiving the current signal that is less than bias current i_(b).This limitation determines the frequency of Ck 316, and ultimately theprocessing speed of ADC 200.

Furthermore, if first and second current signals i₁ 318 and i₂ 320 bothhave values near to that of bias current i_(b) (i.e., small signalcurrent i_(s)), it is possible that the output voltage (at N₄ 310 or N₅312) may not reach LOW or HIGH before the end of the sampling phase. Inthis situation, ADC 200 does not produce a digital output. Such a“non-decision” is referred to as a “bit error”. Bit errors can adverselyeffect the performance of a system that uses the digital output of ADC200. Such systems typically require bit error rates on an order of 10⁻¹⁸to 10⁻¹⁶. Traditionally, bit errors are reduced by cascading latchcomparators, where the overall bit error rate of the system is theproduct of the bit error rate of each cascaded latch comparator.However, this solution delays processing, complicates circuit design,uses additional die area, and consumes more power. Thus, there is a needto decrease the time necessary for the port (i.e., N₄ 310 or N₅ 312)receiving the current signal (i.e., i₁ 318 or i₂ 320) that is greaterthan bias current i_(b) to reach its new steady state voltage.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to high speed latch comparators. In alatch circuit having a bistable pair of cross connected transistors of afirst polarity and a third transistor of a second polarity, a currentsignal greater than a bias current is received at a latch circuit port,amplified with the third transistor, and applied to the latch circuitport. This decreases the time in which the latch circuit port receivingthe current signal greater than the bias current reaches a steady statevoltage. Advantageously, the time in which the latch circuit portreceiving the current signal less than the bias current reaches a steadystate voltage also decreases.

In an embodiment, a latch circuit comprises a bistable pair and avertical latch. The bistable pair is connected between a reset switchand a first supply voltage. The bistable pair has a first port capableof receiving a first current signal and producing a first outputvoltage, and a second port capable of receiving a second current signaland producing a second output voltage. The vertical latch is connectedbetween the first supply voltage and a second supply voltage, andconnected to the bistable pair. The vertical latch acts to decrease thetime necessary for the port receiving the current signal that is greaterthan bias current i_(b) to reach its new steady state voltage.

Preferably, the bistable pair comprises a first MOSFET and a secondMOSFET such that the gate terminal of the first MOSFET is connected tothe drain terminal of the second MOSFET, the gate terminal of the secondMOSFET is connected to the drain terminal of said the MOSFET, and thesource terminals of the first and the second MOSFETs are connected tothe first supply voltage.

Preferably, the vertical latch comprises a first MOSFET current mirrorpair connected to the bistable pair, and a second MOSFET current mirrorpair connected to the first MOSFET current mirror pair. The firstcurrent mirror can comprise a third MOSFET connected to the first MOSFETof the bistable pair. The second current mirror can comprise a fourthMOSFET connected to the third MOSFET. The source terminal of the thirdMOSFET is connected to the first supply voltage. The drain terminal ofthe third MOSFET is connected to the gate terminal of the fourth MOSFET.The source terminal of the fourth MOSFET is connected to the secondsupply voltage. The drain terminal of the fourth MOSFET is connected tothe gate terminal of the third MOSFET, the gate terminal of the firstMOSFET, and the drain terminal of the second MOSFET.

The first current mirror can further comprise a fifth MOSFET connectedto the third MOSFET. The second current minor can further comprise asixth MOSFET connected to the fourth MOSFET. The source terminal of thefifth MOSFET is connected to the first supply voltage. The drainterminal of the fifth MOSFET is connected to the drain terminal of thefourth MOSFET. The gate terminal of the fifth MOSFET is connected to thegate terminal of the third MOSFET and the drain terminal of the fifthMOSFET. The source terminal of the sixth MOSFET is connected to thesecond supply voltage. The drain terminal of the sixth MOSFET isconnected to the drain terminal of the third MOSFET. The gate terminalof the sixth MOSFET is connected to the gate terminal of the fourthMOSFET and the drain terminal of the sixth MOSFET.

The present invention further comprises a method for reducing the powerconsumed by the latch circuit. When the bistable pair and the verticallatch are reset, the third or fourth MOSFET can be held OFF. Afterresetting, the fourth MOSFET can be held OFF when the second MOSFETchanges state from ON to OFF.

In an embodiment, the fourth MOSFET can be held OFF during the resetphase by a vertical latch reset switch connected to the vertical latch.The vertical latch reset switch can comprise a MOSFET connected betweenthe second supply voltage and the vertical latch. During the resetphase, the vertical latch reset switch connects the gate terminal of thefourth MOSFET to the second supply voltage. Preferably, a voltage sourceis connected between the vertical latch reset switch and the secondsupply voltage to decrease the time in which the vertical latch resetswitch turns OFF, which decreases the time in which the vertical latchcan act to decrease the time necessary for the port receiving thecurrent signal that is greater than bias current i_(b) to reach its newsteady state voltage.

In a related embodiment, the latch circuit can further comprise a secondvertical latch connected between the first supply voltage and the secondsupply voltage, and connected to the bistable pair at the second MOSFETof the bistable pair. A second vertical latch reset switch can beconnected to the second vertical latch. A second voltage source can beconnected between the second vertical latch reset switch and the secondsupply voltage.

In a further related embodiment, the fourth MOSFET can be held OFF afterresetting when the second MOSFET changes state from ON to OFF by asecond bistable pair connected to the second supply voltage, thevertical latch, and the second vertical latch. Preferably, the secondbistable pair comprises a first MOSFET and a second MOSFET such that thegate terminal of the first MOSFET is connected to the drain terminal ofthe second MOSFET, the gate terminal of the second MOSFET is connectedto the drain terminal of said the MOSFET, and the source terminals ofthe first and the second MOSFETs are connected to the second supplyvoltage. The drain terminal of the second MOSFET of the second bistablepair is connected to the gate terminal of the fourth MOSFET of thevertical latch. After resetting, when the second MOSFET changes statefrom ON to OFF, the second MOSFET of the second bistable pair turns ONand holds the fourth MOSFET OFF.

In yet a further related embodiment, both the third and fourth MOSFETscan be held OFF during the reset phase by replacing the vertical latchreset switch and the second vertical latch reset switch with a thirdvertical latch reset switch connected to the second bistable pair, thevertical latch, and the second vertical latch. The third vertical latchreset switch can comprise a MOSFET connected between the second bistablepair and the second supply voltage, connected between the vertical latchand the second supply voltage, and connected between the second verticallatch and the second supply voltage. During the reset phase, the thirdvertical latch reset switch disconnects the fourth MOSFET from thesecond supply voltage without connecting the third MOSFET to the secondsupply voltage.

In an alternative embodiment, the third MOSFET can be held OFF duringthe reset phase by a reset circuit connected to the bistable pair, thevertical latch, and the second vertical latch. The reset circuit cancomprise a first MOSFET connected between the bistable pair and thefirst supply voltage, and a second MOSFET connected between the verticallatch and the first supply voltage. During the reset phase, the secondMOSFET of the reset circuit disconnects the third MOSFET from the firstsupply voltage.

The reset switch can comprise a MOSFET connected between the first portand the second port. A clock voltage is applied to the gate terminal ofthe MOSFET. The present invention further comprises a method forreducing the clock voltage where the reset switch comprises a resetcircuit.

In an embodiment, the reset circuit comprises a first MOSFET, a secondMOSFET, and a third MOSFET. The first MOSFET is connected to the firstsupply voltage. The second MOSFET is connected between the first MOSFETand the first port. The third MOSFET is connected between the firstMOSFET and the second port. The clock voltage is applied to the gateterminal of the first MOSFET.

The present invention also includes a comparator comprising an inputstage, a latch circuit, and an output stage. The input stage is capableof receiving an analog signal. The latch circuit is connected to theinput stage. The latch circuit has a bistable pair and a vertical latch.The output stage is connected to the latch circuit. The output stage iscapable of retaining an output of the latch circuit.

BRIEF DESCRIPTION OF THE FIGURES

The accompanying drawings, which are incorporated herein and form partof the specification, illustrate the present invention and, togetherwith the description, further serve to explain the principles of theinvention and to enable a person skilled in the pertinent art to makeand use the invention.

FIG. 1 is a graph 100 that shows the tradeoff between bandwidth anddegree of resolution for the various ADC architectures.

FIG. 2A is a block diagram of an exemplary conventional two-bit flashADC 200.

FIG. 2B is a truth table 244 for priority encoder 208.

FIG. 3 is a schematic diagram of an exemplary conventional latch circuit300 that can be used in an implementation of any of comparators A 202, B204, or C 206.

FIG. 4 is a schematic diagram of a latch circuit 400 that explains thepresent invention.

FIG. 5 is a schematic diagram of a latch circuit 500, in which latchcircuit 400 further comprises a vertical latch reset switch 502.

FIG. 6 is a schematic diagram of a latch circuit 600, in which latchcircuit 500 further comprises a second vertical latch 602 and a secondvertical latch reset switch 604.

FIG. 7 is a schematic diagram of a latch circuit 700, in which latchcircuit 600 further comprises a second bistable pair 702.

FIG. 8 is a schematic diagram of a latch circuit 800, in which resetswitch 304 of latch circuit 700 is replaced by a reset circuit 802.

FIG. 9 shows a flow chart of a method 900 for decreasing the time inwhich a latch circuit port receiving a current signal greater than abias current reaches a steady state voltage.

FIG. 10 is a schematic diagram of a latch circuit 1000, in which latchcircuit 700 further comprises a reset circuit 1002.

FIG. 11 is a schematic diagram of a latch circuit 1100, in which latchcircuit 400 further comprises reset circuit 1002.

FIG. 12 is a schematic diagram of a latch circuit 1200, in which latchcircuit 500 further comprises a voltage source “ΔV₁” 1202.

FIG. 13 is a schematic diagram of a latch circuit 1300, in which latchcircuit 700 further comprises voltage source ΔV₁ 1202 and a secondvoltage source “ΔV₂” 1302.

FIG. 14 is a schematic diagram of a latch circuit 1400, in whichvertical latch reset switch 502 and second vertical latch reset switch604 of latch circuit 700 are replaced by a third vertical latch resetswitch 1402.

FIG. 15 is a graph 1500 of a current 1502 drawn by latch circuit 700 asa function of time “t” 1504 after the voltage of Ck 316 changes from UPto DOWN.

FIG. 16 is a schematic diagram of a comparator 1600 implemented usinglatch circuit 700.

FIG. 17 is a schematic diagram of an alternative embodiment 1700 ofvertical latch 402.

FIG. 18 shows a flow chart of a method 1800 for reducing the powerconsumed by a latch circuit.

The preferred embodiments of the invention are described with referenceto the figures where like reference numbers indicate identical orfunctionally similar elements. Also in the figures, the left-mostdigit(s) of each reference number identify the figure in which thereference number is first used.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to high speed latch comparators. FIG. 4 isa schematic diagram of a latch circuit 400 that explains the presentinvention. Latch circuit 400 comprises bistable pair 302 connectedbetween reset switch 304 and analog ground V_(AG) 218. (Alternatively,analog ground V_(AG) 218 can be replaced by first supply voltageV_(SS).) Preferably, bistable pair 302 comprises first NMOSFET M₁ 306and second NMOSFET M₂ 308 connected in the same manner as in latchcircuit 300. Ideally, M₁ 306 and M₂ 308 are matched transistors.Preferably, each of M₁ 306 and M₂ 308 has a gain greater than one.However, bistable pair 302 can function if the product of the individualgains of M₁ 306 and M₂ 308 (i.e., the loop gain) is greater than one.Preferably, reset switch 304 comprises third NMOSFET M₃ 314. Clockwaveform Ck 316 is applied to the gate terminal of M₃ 314.

A vertical latch 402 is connected between analog ground V_(AG) 218 and asecond supply voltage “V_(DD)” 404. Preferably, vertical latch 402comprises a fourth NMOSFET “M₄” 406 and a first PMOSFET (p-channelMOSFET) “M₅” 408. Ideally, M₄ 406 and M₅ 408 are matched transistors.Preferably, each of M₄ 406 and M₅ 408 has a gain greater than one.However, vertical latch 402 can function if the product of theindividual gains of M₄ 406 and M₅ 408 (i.e., the loop gain) is greaterthan one. The source terminal of M₄ 406 is connected to analog groundV_(AG) 218. The drain terminal of M₄ 406 is connected to the gateterminal of M₅ 408. The gate terminal of M₄ 406 is connected to the gateterminal of M₂ 308. The source terminal of M₅ 408 is connected to secondsupply voltage V_(DD) 404. The drain terminal of M₅ 408 is connected tothe gate terminal of M₄ 406. The skilled artisan will appreciate that M₄406 and M₅ 408 can also be realized in other field effect, junction, orcombination transistor technologies.

In latch circuit 400, when the voltage of Ck 316 is LIP (i.e, the resetphase), M₃ 314 connects N₄ 310 with N₅ 312, so that the steady statevoltages at both nodes are equal, and bias current i_(b) flows througheach of M₁ 306 and M₂ 308. Parasitic capacitances at each of nodes N₄310 and N₅ 312 are charged by bias current i_(b) that flows through eachof M₁ 306 and M₂ 308. Bias current i_(b) charges the parasiticcapacitances at each of nodes N₄ 310 and N₅ 312 so that the voltages atN₄ 310 and N₅ 312 are at MID. The gate and drain terminals of M₁ 306 andM₂ 308 are connected together. M₁ 306 and M₂ 308 are sized so that,under these conditions, they are both ON.

When the voltage of Ck 316 is DOWN (i.e., the sampling phase), thestates of M_(i) 306 and M₂ 308 are controlled by first and secondcurrent signals 318 and i₂ 320. For example, when first current signali₁ 318 is greater than bias current i_(b) and second current signal i₂320 is less than bias current i_(b), a transient is initiated to forceM₁ 306 OFF, while M₂ 308 remains ON. The course of this transientdepends on how first and second current signals i₁ 318 and i₂ 320 changeduring the sampling phase. However, if M₁ 306 is turned OFF and theparasitic capacitances at N₄ 310 are fully charged by first currentsignal i₁ 318 (i.e., at a new steady state), the voltage at N₄ 310 isHIGH and the voltage at N₅ 312 is LOW. The transient can be explained intwo parts. The first part describes the changes that occur while M₁ 306remains ON. The second part depicts the conclusion of the excursionafter M₁ 306 is turned OFF.

When first current signal i₁ 318 is greater than bias current i_(b),first current signal i₁ 318 continues to charge the parasiticcapacitances at N₄ 310, which causes the voltage at N₄ 310 to rise. Thisis indicated by small up-arrow a 322. Contemporaneously, when secondcurrent signal i₂ 320 is less than bias current i_(b), the parasiticcapacitances at N₅ 312 start to discharge, which causes the voltage atN₅ 312 to drop. This is indicated by small down-arrow b 324.

Because the voltage at N₅ 312 is also the voltage at the gate terminalof M₁ 306, the voltage at the gate terminal of M₁ 306 drops by the sameamount as the drop in the voltage at N₅ 312. This is indicated by smalldown-arrow e 330, where small down-arrow e 330 has the same length(i.e., the same change in voltage) as small down-arrow b 324. Becausethe voltage at the source terminal of M₁ 306 is held at analog groundV_(AG) 218, the gate-to-source voltage of M₁ 306 decreases by the sameamount as the drop in the voltage at the gate terminal of M₁ 306. Thedecrease in the gate-to-source voltage of M₁ 306 causes its draincurrent to decrease. In response to the decrease in the gate-to-sourcevoltage of M₁ 306 and the decrease in its drain current, thedrain-to-source voltage of M₁ 306 increases by a greater magnitude thanthe decrease in its gate-to-source voltage. This is indicated by largeup-arrow f 332, where large up-arrow f 332 has a longer length (i.e., alarger change in voltage) than small down-arrow e 330.

Meanwhile, because the voltage at N₄ 310 is also the voltage at the gateterminal of M₂ 308, the voltage at the gate terminal of M₂ 308 rises bythe same amount as the rise in the voltage at N₄ 310. This is indicatedby small up-arrow c 326, where small up-arrow c 326 has the same length(i.e., the same change in voltage) as small up-arrow a 322. Likewise,because the voltage at N₄ 310 is also the voltage at the gate terminalof M₄ 406, the voltage at the gate terminal of M₄ 406 rises by the sameamount as the rise in the voltage at N₄ 310. This is indicated by asmall up-arrow “g” 410, where small up-arrow g 410 has the same length(i.e., the same change in voltage) as small up-arrow a 322.

Because the voltage at the source terminal of M₂ 308 is held at analogground V_(AG) 218, the gate-to-source voltage of M₂ 308 increases by thesame amount as the rise in the voltage at the gate terminal of M₂ 308.The increase in the gate-to-source voltage of M₂ 308 causes its draincurrent to increase. In response to the increase in the gate-to-sourcevoltage of M₂ 308 and the increase in its drain current, thedrain-to-source voltage of M₂ 308 decreases by a greater magnitude thanthe increase in its gate-to-source voltage. This is indicated by largedown-arrow d 328, where large down-arrow d 328 has a longer length(i.e., a larger change in voltage) than small up-arrow c 326. Likewise,because the voltage at the source terminal of M₄ 406 is held at analogground V_(AG) 218, the gate-to-source voltage of M₄ 406 increases by thesame amount as the rise in the voltage at the gate terminal of M₄ 406.The increase in the gate-to-source voltage of M₄ 406 causes its draincurrent to increase. In response to the increase in the gate-to-sourcevoltage of M₄ 406 and the increase in its drain current, thedrain-to-source voltage of M₄ 406 decreases by a greater magnitude thanthe increase in its gate-to-source voltage. This is indicated by a largedown-arrow “h” 412, where large down-arrow h 412 has a longer length(i.e., a larger change in voltage) than small up-arrow c 326.

Because the voltage at the source terminal of M₄ 406 is held at analogground V_(AG) 218, the decrease in the drain-to-source voltage of M₄ 406causes the voltage at the drain terminal of M₄ 406 to drop by the sameamount. Because the voltage at the drain terminal of M₄ 406 is also thevoltage at the gate terminal of M₅ 408, the voltage at the gate terminalof M₅ 408 drops by the same amount as the drop in the voltage at thedrain terminal of M₄ 406. This is indicated by a large down-arrow “j”414, where large down-arrow j 414 has the same length (i.e., the samechange in voltage) as large down-arrow h 412. Because the voltage at thesource terminal of M₅ 408 is held at second supply voltage V_(DD) 404,the drop in the voltage at the gate terminal of M₅ 408 (i.e., a PMOSFET)causes its gate-to-source voltage to increase by the same amount. Theincrease in the gate-to-source voltage of M₅ 408 causes its draincurrent to increase. In response to the increase in the gate-to-sourcevoltage of M₅ 408 and the increase in its drain current, thedrain-to-source voltage of M₅ 408 decreases by a greater magnitude thanthe increase in its gate-to-source voltage. This is indicated by alarger up-arrow “k” 416, where larger up-arrow k 416 has a longer length(i.e., a larger change in voltage) than large down-arrow j 414.

Because the voltage at the source terminal of M₂ 308 is held at analogground V_(AG) 218, the voltage at N₅ 312 drops by the same amount as thedecrease in drain-to-source voltage of M₂ 308. Thus, the voltage at N₅312 drops under the relatively small effect of second current signal i₂320 being less than bias current i_(b) (i.e., small down-arrow b324),and the relatively large effect of the decrease in the drain-to-sourcevoltage of M₂ 308 (i.e., large down-arrow d 328).

Because the voltage at N₄ 310 is also the voltage at the drain terminalof M₅ 408 and because the voltage at the source terminal of M₅ 408 isheld at second supply voltage V_(DD) 404, the voltage at N₄ 310 rises bythe same amount as the decrease in the drain-to-source voltage of M₅408. Furthermore, because the voltage at the source terminal of M₁ 306is held at analog ground V_(AG) 218, the voltage at N₄ 310 rises by thesame amount as the increase in drain-to-source voltage of M₁ 306.Additionally, because the voltage at the source terminal of M₅ 408 isheld at second supply voltage V_(DD) 404, the voltage at N₄ 310 alsorises by the same amount as the decrease in drain-to-source voltage ofM₅ 408 (i.e., a PMOSFET). Thus, the voltage at N₄ 310 rises under therelatively small effect of first current signal i₁ 318 being greaterthan bias current i_(b) (i.e., small up-arrow a 322), the relativelylarge effect of the increase in the drain-to-source voltage of M₁ 306(i.e., large up-arrow f 332), and the relatively larger effect of thedecrease in the drain-to-source voltage of M₅ 408 (i.e., larger up-arrowk 416).

The increasing of the drain-to-source voltage of M₁ 306 and thedecreasing of the drain-to-source voltage of M₂ 308 reinforce eachother. The gate-to-source voltage of M₁ 306 decreases with thedrain-to-source voltage of M₂ 308 until M₁ 306 is turned OFF.

When M₁ 306 is OFF, it does not conduct current. Without drain current,the decreasing of the gate-to-source voltage of M₁ 306 no longer effectsits drain-to-source voltage. However, the voltage at N₄ 310 continues torise under the relatively small effect of first current signal i₁ 318being greater than bias current i_(b) (i.e., small up-arrow a 322) andthe relatively larger effect of the decrease in the drain-to-sourcevoltage of M₅ 408 (i.e., larger up-arrow k 416) until the parasiticcapacitances at N₄ 310 are fully charged and the voltage at N₄ 310 isHIGH.

It will be recognized that M₄ 406 and M₅ 408 foam a positive feedbackloop that amplifies first current signal i₁ 318 and applies anexponentially growing current to the drain terminal of M₁ 306. Thus, theparasitic capacitances at N₄ 310 are charged under the combined effectsof first current signal i₁ 318 and the exponentially growing currentdrawn from second supply voltage V_(DD) 404 by M₅ 408.

Contemporaneously, because the voltage at N₄ 310 is also the voltage atthe gate terminal of M₂ 308, the voltage at the gate terminal of M₂ 308continues to rise. Because M₂ 308 remains ON, the increase in itsgate-to-source voltage causes the drain current of M₂ 308 to increase,which in turn causes its drain-to-source voltage to decrease by agreater magnitude than the increase in the gate-to-source voltage of M₂308. Thus, the voltage at N₅ 312 continues to drop under the relativelysmall effect of second current signal i₂ 320 being less than biascurrent i_(b) (i.e., small down-arrow b 324) and the relatively largeeffect of the decrease in the drain-to-source voltage of M₂ 308 (i.e.,large up-arrow f 332) until the discharge of the parasitic capacitancesat N₅ 312 is balanced and the voltage at N₅ 312 is LOW.

Thus, vertical latch 402 acts (i.e., larger up-arrow k 416) to decreasethe time necessary for the port (i.e., N₄ 310) receiving the currentsignal (i.e., i₁ 318) that is greater than bias current i_(b) to reachits new steady state voltage. Advantageously, the time necessary for theport (i.e., N₄ 310) receiving the current signal (i.e., i₁ 318) that isless than bias current i_(b) to reach a steady state voltage also isdecreased.

FIG. 5 is a schematic diagram of a latch circuit 500, in which latchcircuit 400 further comprises a vertical latch reset switch 502.Preferably, vertical latch reset switch 502 comprises a second PMOSFET“M₆” 504. The source terminal of M₆ 504 is connected to second supplyvoltage V_(DD) 404. The drain terminal of M₆ 504 is connected to thegate terminal of M₅ 408. An inverse clock waveform “Ck.bar” 506 isapplied to the gate terminal of M₆ 504. Ck.bar 506 cycles between DOWNvoltage and UP voltage at the sampling frequency in a manner such thatwhen the voltage of Ck 316 is UP, the voltage of Ck.bar 506 is DOWN, andvice versa. The skilled artisan will appreciate that M₆ 504 can also berealized in other field effect, junction, or combination transistortechnologies. In general, vertical latch reset switch 502 can berealized in a variety of switch technologies, includingmicroelectromechanical embodiments.

When the voltage of Ck.bar 506 is DOWN (i.e., the reset phase), M₆ 504connects the gate terminal of M₅ 408 to second supply voltage V_(DD)404. With the gate and source terminals of M₅ 408 connected together,the gate-to-source voltage of M₅ 408 is made to equal zero, holding M₅408 OFF. This disrupts the latching action of vertical latch 402 so thatbistable pair 302 can assume a state independent of the state ofvertical latch 402.

When the voltage of Ck.bar 506 is DOWN, the voltage of Ck 316 is UP.When the voltage of Ck 316 is UP, M₃ 314 connects N₄ 310 and N₅ 312, sothat the steady state voltages at both nodes are equal. Latch circuit500 is configured so that the voltage at N₄ 310 equals the voltage atthe drain terminal of M₅ 408. Because vertical latch reset switch 502holds M₅ 408 OFF, it does not act to effect the state of bistable pair302. Thus, with the gate and drain terminals of M₁ 306 and M₂ 308connected together, latch circuit 500 is configured so that both M₁ 306and M₂ 308 are ON. Because the gate-to-source voltage of M₂ 308 is alsothe gate-to-source voltage of M₄ 406, and M₆ 504 connects the drainterminal of M₄ 406 to second supply voltage V_(DD) 404 such that thedrain-to-source voltage of M₆ 504 is larger than that of M₂ 308, M₄ 406is also ON.

Thus, by holding M₅ 408 OFF, vertical latch reset switch 502 reduces thepower consumed by vertical latch 402 during the reset phase.

FIG. 6 is a schematic diagram of a latch circuit 600, in which latchcircuit 500 further comprises a second vertical latch 602 and a secondvertical latch reset switch 604. Second vertical latch 602 is connectedbetween analog ground V_(AG) 218 and second supply voltage V_(DD) 404.Preferably, second vertical latch 602 comprises a fifth NMOSFET “M₇” 606and a third PMOSFET “M₈” 608. Ideally, M₇ 606 and M₈ 608 are matchedtransistors. Preferably, each of M₇ 606 and M₈ 608 has a gain greaterthan one. However, second vertical latch 602 can function if the productof the individual gains of M₇ 606 and M₈ 608 (i.e., the loop gain) isgreater than one. The source terminal of M₇ 606 is connected to analogground V_(AG) 218. The drain terminal of M₇ 606 is connected to the gateterminal of M₈ 608. The gate terminal of M₇ 606 is connected to the gateterminal of M₁ 306. The source terminal of M₈ 608 is connected to secondsupply voltage V_(DD) 404. The drain terminal of M₈ 608 is connected tothe gate terminal of M₇ 606. Preferably, second vertical latch resetswitch 604 comprises a fourth PMOSFET “M₉” 610. The source terminal ofM₉ 610 is connected to second supply voltage V_(DD) 404. The drainterminal of M₉ 610 is connected to the gate terminal of M₈ 608. Inverseclock waveform Ck.bar 506 is applied to the gate terminal of M₉ 610. Theskilled artisan will appreciate that M₇ 606, M₈ 608, and M₉ 610 can alsobe realized in other field effect, junction, or combination transistortechnologies. In general, second vertical latch reset switch 604 can berealized in a variety of switch technologies, includingmicroelectromechanical embodiments.

Second vertical latch 602 and second vertical latch reset switch 604operate in the same manner as vertical latch 402 and vertical latchreset switch 502. Whereas vertical latch reset switch 502 disrupts thelatching action of vertical latch 402, second vertical latch resetswitch 604 disrupts the latching action of second vertical latch 602.Likewise, while vertical latch 402 acts to decrease the time necessaryfor the port (i.e., N₄ 310) receiving the current signal (i.e., i₁ 318)that is greater than bias current i_(b) to reach its new steady statevoltage, second vertical latch 602 also acts to decrease the timenecessary for the port (i.e., N₅ 312) receiving the current signal(i.e., i₂ 320) that is greater than bias current i_(b) to reach its newsteady state voltage. Because the time in which either port (i.e., N₄310 or N₅ 312) receiving the current signal (i.e., i₁ 318 or i₂ 320)that is greater than bias current i_(b) reaches its new steady statevoltage is decreased, latch circuit 600 is faster than latch circuit300. This enables the frequency of Ck 316 (and Ck.bar 506) to beincreased, which increases the processing speed of an ADC thatincorporates latch circuit 600. Alternatively, where Ck 316 (and Ck.bar506) is maintained at its original frequency, the bit error rate of asystem that uses an ADC that incorporates latch circuit 600 can beimproved.

FIG. 7 is a schematic diagram of a latch circuit 700, in which latchcircuit 600 further comprises a second bistable pair 702. Preferably,second bistable pair 702 comprises a fifth PMOSFET “M₁₀” 704 and a sixthPMOSFET “M₁₁” 706. Ideally, M₁₀ 704 and M₁₁ 706 are matched transistors.Preferably, each of M₁₀ 704 and M₁₁ 706 has a gain greater than one.However, second bistable pair 702 can function if the product of theindividual gains of M₇ 606 and M₈ 608 (i.e., the loop gain) is greaterthan one. The gate terminal of 706 is connected to the drain terminal ofM₁₀ 704 and to the gate terminal of M₈ 608. The gate terminal of M₁₀ 704is connected to the drain terminal of M₁₁ 706 and to the gate terminalof M₅ 408. The source terminals of M₁₀ 704 and M₁₁ 706 are togetherconnected to second supply voltage V_(DD) 404. The skilled artisan willappreciate that M₁₀ 704 and M₁₁ 706 can also be realized in other fieldeffect, junction, or combination transistor technologies.

When the voltage of Ck.bar 506 is DOWN (i.e., the reset phase), M₆ 504and M₉ 610 connect the gate and drain terminals of M₁₀ 704 and M₁₁ 706together to second supply voltage V_(DD) 404. With the gate and sourceterminals of M₁₀ 704 and M₁₁ 706 both connected to second supply voltageV_(DD) 404, the gate-to-source voltages of M₁₀ 704 and M₁₁ 706 are madeto equal zero, holding M₁₀ 704 and M₁₁ 706 OFF.

When the voltage of Ck.bar 506 is UP (i.e. the sampling phase), thestates of M₁ 306, M₂ 308, M₁₀ 704, and M₁₁ 706 are controlled by firstand second current signals i₁ 318 and i₂ 320. However, in the situationin which first and second current signals i₁ 318 and i₂ 320 both havevalues near to that of bias current i_(b) (i.e., small signal currenti_(s)), there can be a significant delay before first and second currentsignals i₁ 318 and i₂ 320 act to force one MOSFET (e.g., M₁ 306) OFFwhile the other MOSFET (e.g., M₂ 308) remains ON. Contemporaneously,with M₄ 406 and M₇ 606 both ON at the start of the sampling phase, thegate-to-source voltages of M₅ 408 and Mg 608 (i.e., PMOSFETs) can driftto values greater than their threshold voltages such that M₅ 408 and M₈608 turn ON. Having M₁ 308, M₂ 310, M₄ 406, M₅ 408, M₇ 606, and M₈ 608all ON before the MOSFETs change states can cause latch circuit 700 todraw a large amount of current. Latch circuit 700 acts, in response tofirst and second current signals i₁ 318 and i₂ 320, to force one MOSFETof second bistable pair 702 (e.g., M₁₀ 704) ON while the other MOSFET ofsecond bistable pair 702 (e.g., M₁₁ 706) remains OFF. The MOSFET ofsecond bistable pair 702 (e.g., M₁₀ 704) that turns ON connects the gateterminal of its corresponding vertical latch MOSFET (e.g., M₅ 408) tosecond supply voltage V_(DD) 404. With the gate and source terminals ofthe corresponding vertical latch MOSFET connected together, thegate-to-source voltage of the corresponding vertical latch MOSFET ismade to equal zero, holding the corresponding vertical latch MOSFET OFF.In this manner, second bistable pair 702 acts to prevent latch circuit700 from drawing unnecessary current before the MOSFETs change statesduring the sampling phase. Thus, for comparable realizations of latchcircuits 600 and 700, latch circuit 700 consumes less power.

For example, when, at the start of the sampling phase, first currentsignal i₁ 318 is slightly larger than bias current i_(b) (i.e., smallpositive signal current i_(s)), then first current signal i_(i) 318slowly continues to charge the parasitic capacitances at N₄ 310, whichcauses the voltage at N₄ 310 to rise slightly. This is indicated by avery small up-arrow “m” 708. Because the voltage at N₄ 310 is also thevoltage at the gate terminal of M₄ 406, the voltage at the gate terminalof M₄ 406 rises by the same amount as the rise in the voltage at N₄ 310.This is indicated by a very small up-arrow “n” 710, where very smallup-arrow n 710 has the same length (i.e., the same change in voltage) asvery small up-arrow m 708.

Because the voltage at the source terminal of M₄ 406 is held at analogground V_(AG) 218, the gate-to-source voltage of M₄ 406 increases by thesame amount as the rise in the voltage at the gate terminal of M₄ 406.The increase in the gate-to-source voltage of M₄ 406 causes its draincurrent to increase. In response to the increase in the gate-to-sourcevoltage of M₄ 406 and the increase in its drain current, thedrain-to-source voltage of M₄ 406 decreases by a greater magnitude thanthe increase in its gate-to-source voltage. This is indicated by a smalldown-arrow “p” 712, where small down-arrow p 712 has a longer length(i.e., a larger change in voltage) than very small up-arrow n 710.Because the voltage at the source terminal of M₄ 406 is held at analogground V_(AG) 218, the decrease in the drain-to-source voltage of M₄ 406causes the voltage at the drain terminal of M₄ 406 to drop by the sameamount.

Because the voltage at the drain terminal of M₄ 406 is also the voltageat the gate terminal of M₁₀ 704, the voltage at the gate terminal of M₁₀704 drops by the same amount as the drop in the voltage at the drainterminal of M₄ 406. This is indicated by a small down-arrow “q” 714,where small down-arrow q 714 has the same length (i.e., the same changein voltage) as small down-arrow p 712.

Because the voltage at the source terminal of M₁₀ 704 is held at secondsupply voltage V_(DD) 404, the drop in the voltage at the gate terminalof M₁₀ 704 (i.e., a PMOSFET) causes its gate-to-source voltage toincrease by the same amount. The increase in the gate-to-source voltageof M₁₀ 704 causes its drain current to increase. In response to theincrease in the gate-to-source voltage of M₁₀ 704 and the increase inits drain current, the drain-to-source voltage of M₁₀ 704 decreases by agreater magnitude than the decrease in its gate-to-source voltage. Thisis indicated by a large up-arrow “r” 716, where large up-arrow r 716 hasa greater length (i.e., a larger change in voltage) than small downarrow q 714. Because the voltage at the source terminal of M₁₀ 704 isheld at second supply voltage V_(DD) 404, the decrease in thedrain-to-source voltage of M₁₀ 704 (i.e., a PMOSFET) causes the voltageat the drain terminal of M₁₀ 704 to rise by the same amount.

Because the voltage at the drain terminal of M₁₀ 704 is also the voltageat the gate terminal of M₈ 608, the voltage at the gate terminal of M₈608 rises by the same amount as the rise in the voltage at the drainterminal of M₁₀ 704. This is indicated by a large up-arrow “s” 718,where large up-arrow s 718 has the same length (i.e., the same change involtage) as large up-arrow r 716. Because the voltage at the sourceterminal of M₈ 608 is held at second supply voltage V_(DD) 404, the risein the voltage at the gate terminal of M₈ 608 (i.e. a PMOSFET) causesits gate-to-source voltage to decrease by the same amount.

The decrease in the gate-to-source voltage of M₈ 608 ensures that it isless than its threshold voltage so that M₈ 608 is held OFF. Having M₈608 held OFF until first current signal i₁ 318 charges the parasiticcapacitances at N₄ 310 to its new steady state voltage of HIGH preventslatch circuit 700 from drawing unnecessary current during the samplingphase.

Likewise, it can be demonstrated that when, at the start of the samplingphase, second current signal i₂ 320 is slightly larger than bias currenti_(b) (i.e., small negative signal current i_(s)), then second currentsignal i₂ 320 causes M₁₁ 706 to turn ON so that M₅ 408 is held OFF.Having M₅ 408 held OFF until second current signal i₂ 320 charges theparasitic capacitances at N₅ 312 to its new steady state voltage of HIGHprevents latch circuit 700 from drawing unnecessary current during thesampling phase.

Simulations of an implementation that uses an ADC that incorporateslatch circuit 700, in which parameters that define latch circuit 700(i.e., supply voltages, clock frequency, etc.) had specific values,showed latch circuit 700 to be capable of a five-fold increase in speed,or alternatively capable of reducing bit error rate from 10⁻¹⁰ tobetween 10⁻⁸⁰ and 10⁻⁵⁰.

FIG. 8 is a schematic diagram of a latch circuit 800, in which M₃ 314 ofreset switch 304 of latch circuit 700 is replaced by a reset circuit802. Preferably, reset circuit 802 comprises a sixth NMOSFET “M₁₂” 804,a seventh NMOSFET “M₁₃” 806, an eighth NMOSFET “M₁₄” 808, and a ninthNMOSFET “M₁₅” 810. The skilled artisan will appreciate that M₁₂ 804, M₁₃806, M₁₄ 808, and M₁₅ 810 can also be realized in other field effect,junction, or combination transistor technologies. In general, M₁₄ 808and M₁₅ 810 can be realized in a variety of switch technologies,including microelectromechanical embodiments, while M₁₂ 804 and M₁₃ 806can be realized using diodes.

In latch circuit 800, the source terminals of M₁ 306, M₂ 308, M₄ 406,and M₇ 606 are together connected to a third node “N₆” 812. In resetcircuit 802, the gate and drain terminals of M₁₂ 804 are togetherconnected to N₄ 310. The gate and drain terminals of M₁₃ 806 aretogether connected to N₅ 312. The source terminals of M₁₂ 804 and M₁₃806 are together connected to the drain terminal of M₁₄ 808. The drainterminal of M₁₅ 810 is connected to N₆ 812. The source terminals of M₁₄808 and M₁₅ 810 are together connected to analog ground V_(AG) 218.(Alternatively, analog ground V_(AG) 218 can be replaced by first supplyvoltage “V_(SS)”.) Clock waveform Ck 316 is applied to the gate terminalof M₁₄ 808. Inverse clock waveform Ck.bar 506 is applied to the gateterminal of M₁₅ 810.

With the gate and drain terminals of M₁₂ 804 connected together, M₁₂ 804turns ON when its gate-to-source voltage is greater than its thresholdvoltage. Likewise, with the gate and drain terminals of M₁₃ 806connected together, M₁₃ 806 turns ON when its gate-to-source voltage isgreater than its threshold voltage. When the voltage of Ck 316 is UP(i.e., the reset phase), M₁₄ 808 reduces the voltages at the sourceterminals of M₁₂ 804 and M₁₃ 806 so that their gate-to-source voltagesare greater than their threshold voltages and M₁₂ 804 and M₁₃ 806 turnON. When M₁₂ 804 and M₁₃ 806 are ON, they connect N₄ 310 and N₅ 312together. Contemporaneously, when the voltage of Ck.bar 506 is DOWN(i.e., the reset phase), M₁₅ 810 disconnects N₆ 812 from analog groundV_(AG) 218. This insulates bistable pair 302, vertical latch 402, andsecond vertical latch 602 from the connection between N₄ 310 and N₅ 312provided by M₁₂ 804 and M₁₃ 806. The connection between N₄ 310 and N₅312 provided by M₁₂ 804 and M₁₃ 806 causes the steady state voltages atboth nodes to be equal. First and second current signals i₁ 318 and i₂320 flow through M₁₂ 804 and M₁₃ 806, which are sized so that, underthese conditions, their drain-to-source voltages are MID. Thus, thevoltages at N₄ 310 and N₅ 312 are equal to MID.

When the voltage of Ck.bar 506 is UP and the voltage of Ck 316 is DOWN(i.e., the sampling phase), M₁₅ 810 connects N₆ 812 to analog groundV_(AG) 218, M₁₄ 808 raises the voltages at the source terminals of M₁₂804 and M₁₃ 806 so that their gate-to-source voltages are less thantheir threshold voltages and M₁₂ 804 and M₁₃ 806 turn OFF, and latchcircuit 800 operates in the same manner as latch circuit 700 describedabove.

In latch circuits 300, 400, 500, 600, and 700, the source terminal of M₃314 is connected to the drain terminal of one of M₁ 306 or M₂ 308; thedrain terminal of M₃ 314 is connected the drain terminal of the other ofM₁ 306 or M₂ 308. Clock waveform Ck 316 is applied to the gate terminalof M₃ 314. When the voltage of Ck 316 is UP, M₃ 314 connects the gateand drain terminals of M₁ 306 and M₂ 308 together. This requires thatthe UP voltage of Ck 316 be greater than the sum of HIGH and thethreshold voltage of M₃ 314. This can pose a problem when these latchcircuits are realized in integrated circuits with low power supplyvoltages. Advantageously, in latch circuit 800, the source terminals ofM₁₄ 808 and M₁₅ 810 are connected to analog ground V_(AG) 218 so thatthe UP voltage of Ck 316 only needs to be greater than the thresholdvoltages of M₁₄ 808 and M₁₅ 810.

FIG. 9 shows a flow chart of a method 900 for decreasing the time inwhich a latch circuit port receiving a current signal greater than abias current reaches a steady state voltage. The latch circuit comprisesa bistable pair of cross connected transistors of a first polarity, anda third transistor of a second polarity. For example, the drain terminalof a first FET of a first polarity is connected to the gate terminal ofa second FET of the first polarity, the drain terminal of the second FETis connected to the gate terminal of the first FET, the source terminalsof the FETs are connected together, and a third FET of a second polarityis provided. In another example, the collector terminal of a firstjunction transistor of a first polarity is connected to the baseterminal of a second junction transistor of the first polarity, thecollector terminal of the second junction transistor is connected to thebase terminal of the first junction transistor, the emitter terminals ofthe junction transistors are connected together, and a third junctiontransistor of a second polarity is provided.

At a step 902, the current signal greater than the bias current isamplified with the third transistor. At a step 904, the amplifiedcurrent signal is applied to the latch circuit port receiving thecurrent signal greater than the bias current. For example, a currentsignal greater than a bias current (e.g., i₁ 318) is received at a latchcircuit port (e.g., N₄ 310) and continues to charge the parasiticcapacitances at the latch circuit port, which causes the voltage at thelatch circuit port to rise. The voltage at the latch circuit port isamplified by a third transistor (e.g., M₅ 408) so that it draws currentfrom a power supply (e.g., V_(DD) 404). The current drawn from the powersupply is applied to the latch circuit port. Thus, the parasiticcapacitances at the latch circuit port are charged under the combinedeffects of the current signal greater than the bias current and thecurrent drawn from the power supply. This decreases the time in whichthe latch circuit port receiving the current signal greater than thebias current reaches the steady state voltage.

FIG. 10 is a schematic diagram of a latch circuit 1000, in which latchcircuit 700 further comprises a reset circuit 1002. Preferably, resetcircuit 1002 comprises a tenth NMOSFET “M₁₆” 1004 and an eleventhNMOSFET “M₁₇” 1006. The skilled artisan will appreciate that M₁₆ 1004and M₁₇ 1006 can also be realized in other field effect, junction, orcombination transistor technologies. In general, M₁₆ 1004 and M₁₇ 1006can be realized in a variety of switch technologies, includingmicroelectromechanical embodiments.

In latch circuit 1000, the source terminals of M₁ 308 and M₂ 310 aretogether connected to third node N₆ 812, and the source terminals of M₄406 and M₇ 606 are together connected to a fourth node “N₇” 1008. Inreset circuit 1002, the drain terminal of M₁₆ 1004 is connected to N₆812, and the drain terminal of M₁₇ 1006 is connected to N₇ 1008. Thesource terminals of M₁₆ 1004 and M₁₇ 1006 are together connected toanalog ground V_(AG) 218. (Alternatively, analog ground V_(AG) 218 canbe replaced by first supply voltage “V_(SS)”.) Clock waveform Ck 316 isapplied to the gate terminal of M₁₆ 1004. Inverse clock waveform Ck.bar506 is applied to the gate terminal of M₁₇ 1006.

When the voltage of Ck 316 is UP and the voltage of Ck.bar 506 is DOWN(i.e., the reset phase), M₁₆ 1004 connects N₆ 812 to analog groundV_(AG) 218, and M₁₇ 1006 disconnects N₇ 1008 from analog ground V_(AG)218. With the voltages at the source terminals of M₄ 406 and M₇ 606 notheld equal to analog ground V_(AG) 218, the gate-to-source voltages ofM₄ 406 and M₇ 606 are less than their threshold voltages so that M₄ 406and M₇ 606 turn OFF. Having M₄ 406 and M₇ 606 turned OFF prevents themfrom drawing current during the reset phase. Thus, for comparablerealizations of latch circuits 700 and 1000, latch circuit 1000 consumesless power.

When the voltage of Ck.bar 506 is UP and the voltage of Ck 316 is DOWN(i.e., the sampling phase), M₁₆ 1004 disconnects N₆ 812 from analogground V_(AG) 218, and M₁₇ 1006 connects N₇ 1008 to analog ground V_(AG)218, and latch circuit 1000 operates in the same manner as latch circuit700 described above.

FIG. 11 is a schematic diagram of a latch circuit 1100, in which latchcircuit 400 further comprises reset circuit 1002. In latch circuit 1100,the source terminals of M₁ 308 and M₂ 310 are together connected tothird node N₆ 812, and the source terminal of M₄ 406 is connected tofourth node N₇ 1008. When the voltage of Ck 316 is UP and the voltage ofCk.bar 506 is DOWN (i.e., the reset phase), M₁₆ 1004 connects N₆ 812 toanalog ground V_(AG) 218, M₁₇ 1006 disconnects N₇ 1008 from analogground V_(AG) 218, and reset circuit 1102 operates in the same manner asdescribed above. When the voltage of Ck.bar 506 is UP and the voltage ofCk 316 is DOWN (i.e., the sampling phase), M₁₆ 1004 disconnects N₆ 812from analog ground V_(AG) 218, and M₁₇ 1006 connects N₇ 1008 to analogground V_(AG) 218, and latch circuit 1100 operates in the same manner aslatch circuit 400 described above.

FIG. 12 is a schematic diagram of a latch circuit 1200, in which latchcircuit 500 further comprises a voltage source “ΔV₁” 1202. Voltagesource ΔV₁ 1202 is connected between the source terminal of M₆ 504 andsecond supply voltage V_(DD) 404.

When the voltage of Ck.bar 506 is DOWN (i.e., the reset phase), M₆ 504connects the gate terminal of M₅ 408 to voltage source ΔV₁ 1202. Voltagesource ΔV₁ 1202 is set to a voltage level that holds M₅ 408 OFF when thegate terminal of M₅ 408 is connected to voltage source ΔV₁ 1202. Thisdisrupts the latching action of vertical latch 402 so that bistable pair302 can assume a state independent of the state of vertical latch 402 asdescribed above.

However, unlike latch circuit 500, which holds the voltage at the gateterminal of M₅ 408 equal to the voltage of second supply voltage V_(DD)404, latch circuit 1200 holds the voltage at the gate terminal of M₅ 408equal to the difference between the voltages of supply voltage V_(DD)404 and voltage source ΔV₁ 1202. This reduces the time in which M₆ 504changes state from ON to OFF when the voltage of Ck.bar 506 changes fromDOWN to UP (i.e., the sampling phase). In turn, this reduces the time inwhich vertical latch 402 can resume its latching action to decrease thetime necessary for the port (i.e., N₄ 310) receiving the current signal(i.e., i₁ 318) that is greater than bias current i_(b) to reach its newsteady state voltage. The skilled artisan will appreciate that thefunction of voltage source ΔV₁ 1202 could be realized using a variety ofdevices including, but not limited to, a resistor, a diode-connectedMOSFET, or a bias current source.

FIG. 13 is a schematic diagram of a latch circuit 1300, in which latchcircuit 700 further comprises voltage source ΔV₁ 1202 and a secondvoltage source “ΔV₂” 1302. Voltage source ΔV₁ 1202 is connected betweenthe source terminal of M₆ 504 and second supply voltage V_(DD) 404.Second voltage source ΔV₂ 1302 is connected between the source terminalof M₉ 610 and second supply voltage V_(DD) 404.

Second voltage source ΔV₂ 1302 operates in the same manner as voltagesource ΔV₁ 1202. Whereas, when the voltage of Ck.bar 506 changes fromDOWN to UP (i.e., the sampling phase), voltage source ΔV₁ 1202 reducesthe time in which M₆ 504 changes state from ON to OFF, second voltagesource ΔV₂ 1302 reduces the time in which M₉ 610 changes state from ONto OFF. Because the time in which either port (i.e., N₄ 310 or N₅ 312)receiving current signal (i.e., i₁ 318 or i₂ 320) that is greater thanbias current i_(b) reaches its new steady state voltage is decreased,the frequency of Ck 316 (and Ck.bar 506) can be increased. This canincrease the processing speed of an ADC that incorporates latch circuit1300. Alternatively, the bit error rate of a system that uses an ADCthat incorporates latch circuit 1300 can be improved. As is the casewith voltage source ΔV₁ 1202, the function of second voltage source ΔV₂1302 could be realized using a variety of devices.

FIG. 14 is a schematic diagram of a latch circuit 1400, in whichvertical latch reset switch 502 and second vertical latch reset switch604 of latch circuit 700 are replaced by a third vertical latch resetswitch 1402. Preferably, third vertical latch reset switch 1402comprises a seventh PMOSFET “M₁₈” 1404. The skilled artisan willappreciate that M₁₈ 1404 can also be realized in other field effect,junction, or combination transistor technologies. In general, M₁₈ 1404can be realized in a variety of switch technologies, includingmicroelectromechanical embodiments.

In latch circuit 1400, the source terminals of M₅ 408, M₈ 608, M₁₀ 704,and M₁₁ 706 are together connected to a fifth node “N₈” 1406. In thirdvertical latch reset switch 1402, the drain terminal of M₁₈ 1404 isconnected to N₈ 1406. The source terminal of M₁₈ 1404 is connected tosecond supply voltage V_(DD) 404. Clock waveform Ck 316 is applied tothe gate terminal of M₁₈ 1404.

Latch circuit 1400 is configured so that, when the voltage of Ck 316 isDOWN (i.e., the sampling phase), the gate-to-source voltage of M₁₈ 1404(i.e., a PMOSFET) is less than its threshold voltage and M₁₈ 1404 turnsON. When M₁₈ 1404 is ON, it connects N₈ 1406 to second supply voltageV_(DD) 404, and latch circuit 1400 operates in a similar manner as latchcircuit 700 described above.

However, when the voltage of Ck 316 is UP (i.e. the reset phase), thegate-to-source voltage of M₁₈ 1404 (i.e., a PMOSFET) is greater than itsthreshold voltage so that M₁₈ 1404 turns OFF. This reduces the voltageat the source terminals of M₅ 408, M₈ 608, M₁₀ 704, and M₁₁ 706 (i.e.,PMOSFETs) so that their gate-to-source voltages are less than theirthreshold voltages and M₅ 408, M₈ 608, M₁₀ 704, and M₁₁ 706 also turnOFF. In turn, this reduces the voltages at the drain terminals of M₄ 406and M₇ 606 (i.e., NMOSFETs) so that their drain-to-source voltages areless than the differences between their gate-to-source voltages andtheir threshold voltages, and M₄ 406 and M₇ 606 also turn OFF. Having M₄406 and M₇ 606 turned OFF prevents them from drawing current during thereset phase. Thus, for comparable realizations of latch circuits 700 and1400, latch circuit 1400 consumes less power.

FIG. 15 is a graph 1500 of a current 1502 drawn by latch circuit 700 asa function of time “t” 1504 after the voltage of Ck 316 changes from UPto DOWN. Graph 1500 comprises a series of curves including, but notlimited to, a first curve 1506, a second curve 1508, a third curve 1510,and a fourth curve 1512.

At steady state, latch circuit 700 draws current Iv_(DD) 1502 equal tofour times bias current i_(b). Recalling Eqs. (1) and (2), the sum ofthe currents drawn by M₁ 306 and M₂ 308 is equal to twice bias currenti_(b). Additionally, M₄ 406 mirrors the current drawn by M₂ 308, whileM₇ 606 mirrors the current drawn by M₁ 306. (During the sampling phase,the currents drawn by M₄ 406 and M₇ 606 are from the parasiticcapacitances associated with, respectively, M₅ 408 and M₈ 608.)

In latch circuit 700, during the reset phase, M₁ 306, M₂ 308, M₄ 406,and M₇ 606 are turned ON, while M₅ 408, M₈ 608, M₁₀ 704, and M₁₁ 706 areturned OFF. During the sampling phase, the states of M₁ 306 and M₂ 308are controlled by first and second current signals i₁ 318 and i₂ 320.For example, if first current signal i₁ 318 is greater than bias currenti_(b), M₁ 306 turns OFF while M₂ 308 remains ON. Under these conditions,at steady state, M₅ 408 and M₁₀ 704 also turn ON, while M₇ 606 turnsOFF. M₄ 406 remains ON, and M₈ 608 and M₁₁ 706 remain OFF. However,although M₅ 408 and M₁₀ 704 are ON, because M₁ 306 and M₇ 606 are OFF,latch circuit 700 does not draw any additional current Iv_(DD) 1502. Ingraph 1500, this situation is indicated by first curve 1506, whichequals a steady state current of four times bias current i_(b).

As mentioned above, the time in which M₁ 306 and M₂ 308 change states isa function of the sizes of first and second current signals i₁ 318 andi₂ 320. If the current signal (e.g., i₁ 318 or i₂ 320) received at theport (e.g., N₄ 310 or N₅ 312) of the MOSFET changing state from ON toOFF is sufficiently large, the port reaches its new steady state voltagerelatively quickly, and the appropriate MOSFETs of latch circuit 700also change states relatively quickly. Thus, during a relatively quicktransient, again no additional current Iv_(DD) 1502 is drawn by latchcircuit 700. This situation is indicated by second curve 1508, whichalso equals a steady state current of four times bias current i_(b).

However, if the time of the transient becomes longer, latch circuit 700acts to decrease the time needed for the port (e.g., N₄ 310 or N₅ 312)receiving the current signal (e.g., i₁ 318 or i₂ 320) greater than biascurrent i_(b) to reach its new steady state voltage. In this situation,latch circuit 700 draws current Iv_(DD) 1502 as charted by, for example,third curve 1510. As indicated by the shape of third curve 1510, currentIv_(DD) 1502 drawn by latch circuit 700 increases at a relatively slowrate, reaches a peak value 1514, then decreases relatively quickly. Peakvalue 1514 is reached when the latching action of latch circuit 700occurs.

If the time of the transient becomes increasingly longer, latch circuit700 draws current Iv_(DD) 1502 for a longer period of time, as chartedby, for example, fourth curve 1512. As indicated by the shape of fourthcurve 1512, current Iv_(DD) 1502 drawn by latch circuit 700 increases atthe same rate as indicated by third curve 1510. However, current Iv_(DD)1502 is drawn for a longer period of time resulting in fourth curve 1512having a higher peak value 1516.

Graph 1500 shows how latch circuit 700 decreases the time needed for theport (e.g., N₄ 310 or N₅ 312) receiving the current signal (e.g., i₁ 318or i₂ 320) greater than bias current i_(b) to reach its new steady statevoltage, while limiting the power consumed to realize this decrease intime. Latch circuit 700 only draws current Iv_(DD) 1502 in thosesituations in which first and second current signals i₁ 318 and i₂ 320both have values near to that of bias current i_(b) (i.e., small signalcurrent i_(s)).

Of note, each curve of graph 1500 is separated from its next curve by anequal separation in time “Δt” 1518. However, each curve represents aten-fold magnitude increase in current signal (e.g., i₁ 318 or i₂ 320)over the next curve to the right. For example, current signal (e.g., i₁318 or i₂ 320) for curve 1510 is one-thousand times greater than currentsignal (e.g., i₁ 318 or i₂ 320) for curve 1512.

FIG. 16 is a schematic diagram of a comparator 1600 implemented usinglatch circuit 700. Comparator 1600 comprises an input stage 1602, alatch circuit 1604, and an output stage 1606. Preferably, input stage1602 comprises a differential amplifier 1608, a first current mirror1610, and a second current mirror 1612.

Preferably, differential amplifier 1608 comprises a differential pair1614 and a current source 1616. Preferably, differential pair 1614comprises amplifying MOSFETs “M₁₉” 1618 and “M₂₀” 1620. Preferably,current source 1616 comprises biasing MOSFETs “M₂₁” 1622 and “M₂₂” 1624.A biasing MOSFET is connected to the source terminal of each amplifyingMOSFET. The drain terminal of “M₂₁” 1622 is connected to the sourceterminal of M₁₉ 1618; the drain terminal of “M₂₂” 1624 is connected tothe source terminal of M₂₀ 1620. The drain terminals of M₂₁ 1622 and M₂₂1624 are also connected together. The source terminals of M₂₁ 1622 andM₂₂ 1624 are together connected to analog ground V_(AG) 218.(Alternatively, analog ground V_(AG) 218 can be replaced by first supplyvoltage “V_(SS)”.) A load MOSFET is connected to the drain terminal ofeach amplifying MOSFET. The drain terminal of “M₂₃” 1626 is connected tothe drain terminal of M₁₉ 1618; the drain terminal of “M₂₄” 1628 isconnected to the drain terminal of M₂₀ 1620. The source terminals of M₂₃1626 and M₂₄ 1628 are together connected to second supply voltage V_(DD)404.

Preferably, first current mirror 1610 comprises a MOSFET “M₂₅” 1630, andsecond current mirror 1612 comprises a MOSFET “M₂₆” 1632. The sourceterminals of M₂₅ 1630 and M₂₆ 1632 are together connected to secondsupply voltage V_(DD) 404. The gate terminal of M₂₅ 1630 is connected tothe gate and drain terminals of M₂₃ 1626; the gate terminal of M₂₆ 1632is connected to the gate and drain terminals of M₂₄ 1628. In input stage1602, M₁₉ 1618, M₂₀ 1620, M₂₁ 1622, and M₂₂ 1624 are NMOSFETs, while M₂₃1626, M₂₄ 1628, M₂₅ 1630, and M₂₆ 1632 are PMOSFETs. However, thisconfiguration can be reversed depending upon the overall configurationof comparator 1600.

The voltage of analog signal x 228 is received by input stage 1602 at afirst input port “P₁” 1634, which is the noninverting terminal ofcomparator 1600 (e.g., A 202, B 204, or C 206). This allows the voltageof analog signal x 228 to be compared with the reference voltagereceived at second input port “P₂” 1636, which is the inverting terminalof comparator 1600. For example, the voltage of analog signal x 228 iscompared with V/4, for comparator A 202; V/2, for comparator B 204; and3V/4, for comparator C 206. First input port P_(i) 1634 is connected tothe gate terminals of M₁₉ 1618 and M₂₁ 1622. Second input port P₂ 1636is connected to the gate terminals of M₂₀ 1620 and M₂₂ 1624.

Differential pair 1614 (i.e., M₁₉ 1618 and M₂₀ 1620) acts to control thedistribution of current flowing through current source 1616 (e.g., M₂₁1622 and M₂₂ 1624). The sum of the current flowing through both M₁₉ 1618and M₂₀ 1620 equals the current provided by current source 1616. Forexample, as the voltage received at first input port P_(i) 1634 riseswith respect to the voltage received at second input port P₂ 1636, theportion of the total current that flows through M₁₉ 1618 and M₂₃ 1626increases, while the portion of the total current that flows through M₂₀1620 and M₂₄ 1628 decreases. M₂₅ 1630 mirrors the increase in currentflowing through M₂₃ 1626 to produce first current signal i₁ 318 at thedrain terminal of M₂₅ 1630. M₂₆ 1632 mirrors the decrease in currentflowing through M₂₄ 1628 to produce second current signal i₂ 320 at thedrain terminal of M₂₆ 1632.

In the above explanation, differential amplifier 1608 is configured sothat the voltage of analog signal x 228 provides bias for M₂₁ 1622 ofcurrent source 1616, while the reference voltage provides bias for M₂₂1624 of current source 1616. The skilled artisan will appreciate thatdifferential amplifier 1608 can also be configured with a traditionalcurrent source that is independently biased (i.e., the bias is notprovided by the voltage of analog signal x 228 or the referencevoltage).

Latch circuit 1604 comprises latch circuit 700, a third current mirror1638, and a fourth current mirror 1640. Preferably, third current mirror1638 comprises a MOSFET “M₂₇” 1642, and fourth current mirror 1640comprises a MOSFET “M₂₈” 1644. The source terminals of M₂₇ 1642 and M₂₈1644 are together connected to second supply voltage V_(DD) 404. Thegate terminal of M₂₇ 1642 is connected to the gate terminal of M₅ 408;the gate terminal of M₂₈ 1644 is connected to the gate terminal of M₈608. In comparator 1600, latch circuit 700 can be replaced by any oflatch circuits 800, 1000, 1300, or 1400. In latch circuit 1604, M₂₇ 1642and M₂₈ 1644 are PMOSFETs. However, depending upon the overallconfiguration of comparator 1600, they can be NMOSFETs.

First current signal i₁ 318 and second current signal i₂ 320 arereceived at, respectively, N₄ 310 and N₅ 312 and are processed by latchcircuit 700 as described above. M₂₇ 1642 mirrors the current flowingthrough M₅ 408 to produce a third current signal “i₃” 1646 at the drainterminal of M₂₇ 1642. M₂₈ 1644 mirrors the current flowing through M₈608 to produce a fourth current signal “i₄” 1648 at the drain terminalof M₂₈ 1644. Third current signal i₃ 1646 and fourth current signal i₄1648 are proportional to, respectively, the voltages at N₄ 310 and N₅312 (i.e., either HIGHER or LOWER).

Preferably, output stage 1606 comprises a hold latch 1650. Preferably,hold latch 1650 comprises a third bistable pair 1652 and a fourthbistable pair 1654. Preferably, third bistable pair 1652 comprises afirst MOSFET “M₂₉” 1656 and a second MOSFET “M₃₀” 1658. The gateterminal of M₃₀ 1658 is connected to the drain terminal of M₂₉ 1656 at afirst port “N₉” 1660. The gate terminal of M₂₉ 1656 is connected to thedrain terminal of M₃₀ 1658 at a second port “N₁₀” 1662. The sourceterminals of M₂₉ 1656 and M₃₀ 1658 are together connected to secondsupply voltage V_(DD) 404. Preferably, fourth bistable pair 1654comprises a third MOSFET “M₃₁” 1664 and a fourth MOSFET “M₃₂” 1666. Thegate terminal of M₃₂ 1666 is connected to the drain terminal of M₃₁ 1664at first port N₉ 1660. The gate terminal of M₃₁ 1664 is connected to thedrain terminal of M₃₂ 1666 at second port N₁₀ 1662. The source terminalsof M₃₁ 1664 and M₃₂ 1666 are together connected to analog ground V_(AG)218. (Alternatively, analog ground V_(AG) 218 can be replaced by firstsupply voltage “V_(SS)”.) In output stage 1606, M₂₉ 1656 and M₃₀ 1658are PMOSFETs, while M₃₁ 1664 and M₃₂ 1666 are NMOSFETs. However, thisconfiguration can be reversed depending upon the overall configurationof comparator 1600.

Third current signal i₃ 1646 is received at N₉ 1660, while fourthcurrent signal i₄ 1648 is received at N₁₀ 1662. Typically, output stage1606 is followed by digital logic circuits. Sometimes when latch circuit1604 is resetting, the voltages at N₄ 310 and N₅ 312 are neither HIGHERnor LOWER, but some value in between. This can cause problems in thedigital logic circuits. Hold latch 1650 retains the output of latchcircuit 1604 prior to reset, which is either HIGHER or LOWER. Thus,output stage 1606 serves as a buffer between latch circuit 1604 and thedigital logic circuits.

Another advantage of vertical latch circuit 402 can be observed bycomparing it with hold latch 1650. In hold latch 1650, the sum of thegate-to-source voltage of M₂₉ 1656 and the gate-to-source voltage of M₃₁1664 is equal to the difference between V_(DD) 404 and V_(AG) 218.Implementations of hold latch 1650 must take this relationship intoconsideration. In contrast, for the same values of V_(DD) 404 and V_(AG)218, each of M₄ 406 and M₅ 408 can realize a gate-to-source voltage thatis larger than that of M₂₉ 1656 or M₃₁ 1664. Alternatively, by usingvertical latch 402, the difference between V_(DD) 404 and V_(AG) 218 canbe reduced, which can reduce the power consumed.

FIG. 17 is a schematic diagram of an alternative embodiment 1700 ofvertical latch 402. Preferably, vertical latch 1700 comprises a firstcurrent minor pair 1702 and a second current mirror pair 1704.Preferably, first current minor pair 1702 comprises NMOSFET M₄ 406 and atwelfth NMOSFET “M₃₃” 1706. Preferably second current mirror pair 1704comprises PMOSFET M₅ 408 and an eighth PMOSFET “M₃₄” 1708. The skilledartisan will appreciate that M₃₃ 1706 and M₃₄ 1708 can also be realizedin other field effect, junction, or combination transistor technologies.M₃₃ 1706 and M₃₄ 1708 can also be realized using diodes.

In first current minor pair 1702, the drain and gate terminals of M₃₃1706 are connected together, the gate terminal of M₃₃ 1706 is connectedto the gate terminal of M₄ 406, the drain terminal of M₃₃ 1706 isconnected to the drain terminal of M₅ 408, and the source terminals ofM₃₃ 1706 and M₄ 406 are together connected to analog ground V_(AG) 218.In second current pair 1704, the drain and gate terminals of M₃₄ 1708are connected together, the gate terminal of M₃₄ 1708 is connected tothe gate terminal of M₅ 408, the drain terminal of M₃₄ 1708 is connectedto the drain terminal of M₄ 406, and the source terminals of M₃₄ 1708and M₅ 408 are together connected to second supply voltage V_(DD) 404.

M₄ 406, M₅ 408, M₃₃ 1706, and M₃₄ 1708 are sized so that the product ofthe current gain of first current mirror pair 1702 and the current gainof second current minor pair 1704 (i.e., the loop gain of vertical latch1700) is greater than one. This ensures that vertical latch 1700 willhave a latching action. Vertical latch 1700 can also be an alternativeembodiment for second vertical latch 602, with M₄ 406 replaced by M₇606, and M₅ 408 replaced by M₈ 608.

Diode-connected M₃₃ 1706 and M₃₄ 1708 provide vertical latch 1700 withseveral advantages. They provide bias voltages for, respectively, M₄ 406and M₅ 408. This is particularly important for M₅ 408, which, absentvertical latch reset switch 502, lacks a bias voltage necessary tooperate during the sampling phase.

Furthermore, the skilled artisan will appreciate that including verticallatch 402 in latch circuit 400 complicates problems with controlling thedynamic offset voltages in the latch circuit. These problems areparticularly troublesome in vertical latch 402 because it comprises bothNMOSFET M₄ 406 and PMOSFET M₅ 408, and therefore entails thedifficulties associated with matching different MOSFET types. (In latchcircuit 600, the difficulties arise in matching corresponding MOSFETs(i.e., M₄ 406 with M₇ 606, and M₅ 408 with M₃ 608).) However,diode-connected M₃₃ 1706 and M₃₄ 1708 can be sized to bias,respectively, M₄ 406 and M₅ 408 in a manner that corrects thedetrimental effects of their offset voltages.

Additionally, while each of the various latch circuit configurationspresented above is designed to decrease the time necessary for the port(i.e., N₄ 310 or N₅ 312) receiving the current signal (i.e., i₁ 318 ori₂ 320) that is greater than bias current i_(b) to reach its new steadystate voltage, several of the configurations are also designed to limitthe power consumed while realizing this decrease in time.Diode-connected M₃₃ 1706 and M₃₄ 1708 enable a designer to bias,respectively, M₄ 406 and M₅ 408 in a manner that controls when they willchange states during a transient. This allows the designer to balancethe competing needs for decreasing the time necessary for the latchcircuit to reach steady state and limiting the power consumed by thelatch circuit.

FIG. 18 shows a flow chart of a method 1800 for reducing the powerconsumed by a latch circuit. The latch circuit comprises a bistable pairand a vertical latch, wherein the bistable pair has a first MOSFET(e.g., M₁ 306) and a second MOSFET (e.g., M₂ 308) configured so that thedrain terminal of the first MOSFET is connected to the gate terminal ofthe second MOSFET at a first port (e.g., N₄ 310), the drain terminal ofthe second MOSFET is connected to the gate terminal of the first MOSFETat a second port (e.g., N₅ 312), and the source terminals of the firstand second MOSFETs are connected together, and wherein the verticallatch has a third MOSFET (e.g., M₄ 406) and a fourth MOSFET (e.g., M₅408) configured so that the gate terminal of the third MOSFET isconnected to the gate terminal of the second MOSFET and the drainterminal of the fourth MOSFET, and the gate terminal of the fourthMOSFET is connected to the drain terminal of the third MOSFET.

At a step 1802, the bistable pair and vertical latch are reset. In onealternative, at a step 1804, the fourth MOSFET is held OFF during theresetting, thereby reducing the power consumed by the latch circuitduring the resetting. For example, the voltage at the source terminal ofthe fourth MOSFET (e.g., M₅ 408) is held constant, while the voltage atthe gate terminal of the fourth MOSFET is changed, so that the fourthMOSFET is held OFF during the resetting. In another example, the voltageat the drain terminal of the fourth MOSFET (e.g., M₅ 408) is heldconstant, while the voltage at the source terminal of the fourth MOSFETis changed, so that the fourth MOSFET is held OFF during the resetting.

In another alternative, at a step 1806, the third MOSFET is held OFFduring the resetting, thereby reducing the power consumed by the latchcircuit during the resetting. For example, the voltage at the gateterminal of the third MOSFET (e.g., M₄ 406) is held constant, while thevoltage at the source terminal of the third MOSFET is changed, so thatthe third MOSFET is held OFF during the resetting. In another example,the voltage at the source terminal of the third MOSFET (e.g., M₄ 406) isheld constant, while the voltage at the drain terminal of the thirdMOSFET is changed, so that the third MOSFET is held OFF during theresetting.

In yet another alternative, at a step 1808, after the resetting, thefourth MOSFET is held OFF when the second MOSFET changes state from ONto OFF, thereby reducing the power consumed by the latch circuit afterthe resetting. For example, after the resetting, the voltage at thesource terminal of the fourth MOSFET (e.g., M₅ 408) is held constant,while the voltage at the gate terminal of the fourth MOSFET is changed,so that the fourth MOSFET is held OFF when the second MOSFET changesstate from ON to OFF.

CONCLUSION

While various embodiments of the present invention have been describedabove, it should be understood that they have been presented by way ofexample, and not limitation. It will be apparent to persons skilled inthe relevant art that various changes in form and detail can be madetherein without departing from the spirit and scope of the invention.Thus the present invention should not be limited by any of theabove-described exemplary embodiments, but should be defined only inaccordance with the following claims and their equivalents.

1. A bistable latch circuit, comprising: a first port to receive a firstinput current signal and produce a first output voltage signal; a secondport to receive a second input current signal and produce a secondoutput voltage signal; and a vertical latch connected to the first portto provide a feedback signal to the first port based on the first outputvoltage signal; wherein the first port reaches a steady state valuebased on the first and second input current signals and the feedbacksignal.
 2. The bistable latch circuit of claim 1, wherein the feedbacksignal is a feedback voltage signal.
 3. The bistable latch circuit ofclaim 1, wherein the feedback signal is a feedback current signal. 4.The bistable latch circuit of claim 3, wherein the feedback currentsignal grows exponentially.
 5. The bistable latch circuit of claim 1,further comprising a latch reset switch connected to the vertical latchto disrupt the latching action of the vertical latch and reduce powerconsumption of the vertical latch during a reset phase.
 6. The bistablelatch circuit of claim 5, further comprising a voltage source associatedwith the latch reset switch to reduce the time in which the verticallatch resumes its latching action.
 7. The bistable latch circuit ofclaim 1, further comprising a second vertical latch connected to thesecond port to receive the second output voltage signal and provide asecond feedback signal to the second port based on the second outputvoltage signal.
 8. The bistable latch circuit of claim 1, wherein thefirst and second output voltages reach steady state values based onparasitic capacitances.
 9. The bistable latch circuit of claim 1,wherein the vertical latch enables at least one of: an increased clockfrequency and an improved bit error rate (BER) associated with thebistable latch circuit.
 10. An analog-to-digital converter, comprising:a comparator having a first input to receive an analog signal and asecond input to receive a reference signal, the comparator producing adigital signal and including a bistable latch circuit including: a firstport to receive a first input current signal and produce a first outputvoltage signal; a second port to receive a second input current signaland produce a second output voltage signal; and a vertical latchconnected to the first port to provide a feedback signal to the firstport based on the first output voltage signal; wherein the first portreaches a steady state value based on the first and second input currentsignals and the feedback signal.
 11. The bistable latch circuit of claim10, wherein the feedback signal is a feedback voltage signal.
 12. Thebistable latch circuit of claim 10, wherein the feedback signal is afeedback current signal.
 13. The bistable latch circuit of claim 12,wherein the feedback current signal grows exponentially.
 14. Thebistable latch circuit of claim 10, further comprising a latch resetswitch connected to the vertical latch to disrupt the latching action ofthe vertical latch and reduce power consumption of the vertical latchduring a reset phase.
 15. The bistable latch circuit of claim 14,further comprising a voltage source associated with the latch resetswitch to reduce the time in which the vertical latch resumes itslatching action.
 16. The bistable latch circuit of claim 10, furthercomprising a second vertical latch connected to the second port toreceive the second output voltage signal and provide a second feedbacksignal to the second port based on the second output voltage signal. 17.The bistable latch circuit of claim 10, wherein the first and secondoutput voltages reach steady state values based on parasiticcapacitances.
 18. The bistable latch circuit of claim 10, wherein thevertical latch enables at least one of: an increased clock frequency andan improved bit error rate (BER) associated with the bistable latchcircuit.
 19. A flash analog-to-digital converter, comprising: a voltageladder to provide a plurality of reference voltages; an input stage toproduce a differential current signal associated with each of theplurality of reference voltages and an input analog signal, eachdifferential current signal including first and second input currentsignals; and a plurality of latch comparators each receiving the firstand second input current signals and producing a digital output signal,wherein each latch comparator includes: a first port to receive thefirst input current signal and produce a first output voltage signal; asecond port to receive a second input current signal and produce asecond output voltage signal; and a vertical latch connected to thefirst port to provide a feedback signal to the first port based on thefirst output voltage signal; wherein the first port reaches a steadystate value based on the first and second input current signals and thefeedback signal.
 20. The flash analog-to-digital converter of claim 19,wherein the vertical latch enables at least one of: an increased clockfrequency and an improved bit error rate (BER) associated with thebistable latch circuit.